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1 features ? multiband transceiver: 400 mhz to 950 mhz monochip rf solution: transmitter-receiver-synthesizer integrated pll and vco: no external coil very resistant to interferers by design digital channel selection 200 hz steps data rates up to 64 kbps with data clock and no manchester encoding required high output power allowing very low cost printed antennas: ? +10 dbm in the 915 mhz frequency band ? +12 dbm in the 868 mhz frequency band ? +14 dbm in the 433 mhz frequency band fsk modulation: integrated modulator and demodulator power savings: ? stand alone "sleep" mode and "wake-up" procedures ? 8 selectable digital levels for output power ? high data rate and fast settling time of the pll ? oscillator running mode "ready to start" ? analog fsk discriminator allowing measurement and correction of frequency drifts 100% digital interface through r/w registers including: ? digital rssi ?v cc readout description the AT86RF211 (aka: trx01) is a single chip transceiver dedicated to low power wireless applications, optimized for licence-free ism band operations from 400 mhz to 950 mhz. its flexibility and unique level of integration make it a natural choice for any system related to telemetry, remote controls, alarms, radio modems, automatic meter reading, hand held terminals, high-tech toys, etc. the AT86RF211 makes bidirec- tional communications affordable for applications such as secured transmissions with hand-shake procedures, new features and services, etc. the AT86RF211 can easily be configured to provide the optimal solution for the user?s application: choice of exter- nal filters vs. technical requirements (bandwidth, selectivity, immunity, range, etc), and software protocol (single channel, multiple channel, fhss). the AT86RF211 is also well adapted to battery operated systems, as it can be powered with only 2.4v. it also offers a ?wake up? receiver feature to save power by alerting the associated micro- controller only when a valid inquiry is detected. fsk transceiver for ism radio applications AT86RF211 (aka: trx01) rev. 1942c?wire?06/02
2 AT86RF211 1942c?wire?06/02 general overview general overview of functioning the AT86RF211 is a microcontroller rf peripheral: all the user has to do is to write/read registers to setup the chip (i.e. frequency selection) or have information about parame- ters such as rssi level, vbattery, pll lock state. all these operations are carried out via a three-wire serial interface. normal mode thechipisset-upbythe microcontroller: frequency and mode (rx or tx). then it acts like a "pipe": any data entering datamsg is immediately radiated (tx) or any wanted signal collected by the aerial is demodulated, transferred to the microcontroller by the same pin datamsg (rx) as reshaped bits. no data is stored or processed into the chip. see figure 1. note: in rx mode, a clock recovery dataclk is available on the digital interface to provide the microcontroller with a synchronization signal. wake-up mode the chip is set up in a special rx mode called sleep mode. the chip wakes up periodi- cally thanks to its internal timer (stand alone procedure, the microcontroller is in power- down mode), waiting for an expected message previously defined. if no correct sequence is received, the periodic scan continues. if a correct message is detected, its data field is stored into the AT86RF211 (up to 32 bits) and an interrupt is generated on the wakeup pin. see figure 2 and figure 3.
3 AT86RF211 1942c?wire?06/02 figure 1. reception and transmit mode f = frequency of transmitted signal AT86RF211 acts like a "pipe" (data is transmitted with no processing): automatic data to frequency conversion. - datamsg = 0: f = f0 - datamsg = 1: f = f1 AT86RF211 (trx01) transmit mode 3 companion microcontroller datamsg sle, sck, sdata (for set-up) f = frequency of received signal AT86RF211 also acts like a "pipe": data (collected by the antenna) is available on pin datamsg: AT86RF211 (trx01) receive mode 3 companion microcontroller datamsg sle, sck, sdata (for set-up) dataclk datamsg dataclk
4 AT86RF211 1942c?wire?06/02 figure 2. wake-up overview figure 3. periodical scan header + address step 3 : if a correct header is received (mandatory) and address matches (if any), the data field is then stored into AT86RF211 and wakeup pin is activated (to wake-up the microcontroller). the microcontroller will then read the data into one of its registers, and begin a relevant procedure. note : data field is optional: the chip can be simply woken-up with no dedicated data. AT86RF211 (trx01) wake-up mode 3 companion microcontroller wakeup pin step 2 : the chip wakes-up periodically, waiting for an expected message (stand-alone operation) step 1 : the chip is set up in sleep mode using the 3-wire interface (sle, sck, sdata), then microcontroller goes to sleep, waiting for an interrupt on wakeup pin data stored data field reception mode short reception window oscillator settling sleep mode wake up period timing power consumption
5 AT86RF211 1942c?wire?06/02 block diagram figure 4. AT86RF211 block diagram synthesizer frequency ctrl control logic wake-up data slicer bandwidth ctrl rssi level fm discriminator optional filter if2 filter 455 khz pwr ctrl tx pa optional these are the only blocks that depend on the selected ism band (433, 868 or 915 mhz): dual band applications can be done by only switching them. synthesizer, loop filter, if filter(s), power supply decoupling are identical. gain min/max rx aerial matching circuit data msg data clk sdata wake-up sle sck if2 amp if1 amp mixer2 if1 filter 10.7 mhz or 21.4 mhz lna mixer1 tx/rx rf filter rpower osc 10.245 mhz or 20.945 mhz
6 AT86RF211 1942c ? wire ? 06/02 pin description notes: 1. all v cc pins must be connected in each functional mode (tx, rx, wake-up, pdn) 2. to be connected: rxmodeonly,allbut:1,3,17,20,48 tx mode only, all but: 15 to 17, 20, 25 to 27, 30 to 36, 45, 48 3. pin 20 must remain unconnected or connected to ground table 1. pinout pin name comments pin name comments 1 rpower full scale output power resistor 25 skfilt threshold for data slicer 2 txgnd1 gnd 26 dsin data slicer input 3 rf rf input/output 27 discout discriminator output 4 txgnd2 gnd 28 if2vcc vcc 5 txgnd3 gnd 29 if2gnd gnd 6 txgnd4 gnd 30 if2in if2 amplifier input 7 txvcc vcc 31 if2dec 2.2 nf to ground 8 txgnd5 gnd 32 discfilt discriminator bypass 9 dignd gnd 33 if2out if2 mixer output 10 divcc vcc 34 if1dec 4.7 nf to ground 11 datamsg input/output digital message 35 if1in if1 amplifier input 12 sle serial interface enable 36 if1out if1 mixer output 13 sck serial interface clock 37 agnd gnd 14 sdata serial interface data 38 avcc vcc 15 wakeup wake-up output 39 cvcc2 vcc 16 dataclk data clock recovery 40 cgnd2 gnd 17 ? test pin: do not connect 41 filt1 synthesizer output 18 evcc1 vcc 42 vcoin synthesizer input (vco) 19 egnd1 gnd 43 evcc2 vcc 20 ? test pin: do not connect 44 egnd2 gnd 21 cgnd1 gnd 45 rxin lna input from saw filter 22 cvcc1 vcc 46 rxvcc vcc 23 xtal1 crystal input 47 rxgnd gnd 24 xtal2 crystal output 48 swout switch output
7 AT86RF211 1942c ? wire ? 06/02 detailed description frequency synthesis crystal reference oscillator the reference clock is based on a classical colpitts architecture with three external capacitors. an xtal with load capacitor in the range of 10 pf - 20 pf is recommended. the bias circuitry of the oscillator is optimized to produce a low drive level for the xtal. this reduces xtal aging. any standard, parallel mode 10.245 mhz or 20.945 mhz crystal canbeused. note: the pll is activated only when the oscillator is stabilized. figure 5. crystal oscillator inputs figure 6. typical networks notes: 1. various load capacitance (c l ) crystals can be used. in case c l differs of 16 pf or 20 pf, the surrounding network (c1, c2) must be re-calculated. 2. thanks to the fine steps of the synthesizer (200 hz), the trimmer capacitor can be replaced by a software adjustment. synthesizer a high-speed, high-resolution multi-loop synthesizer is integrated. the synthesizer can operate within two frequency bands: 400 mhz to 480 mhz and 800 mhz to 950 mhz. all channels in these two bands can be selected through software programming (registers f0 to f3). all circuitry is on-chip with the exception of the pll loop filter. the phase comparison is made thanks to a charge pump topology. typical charge pump current is 225 a. xtal1 xtal2 c1 = 82 pf c2 = 56 pf xtal1 xtal2 c l = 16 pf 15 pf 6.5/30 pf c1 = 68 pf xtal1 xtal2 c l = 20 pf 33 pf 6.5/30 pf c2 = 68 pf (1) (2) (1) (2)
8 AT86RF211 1942c ? wire ? 06/02 figure 7. synthesizer loop filter schematic note: the pll loop filter can be designed to optimize the phase noise around the carrier. three configurations can be suggested, regarding the application and channel spacing: - narrow band: (14.7 k ? + 2.2 nf) // 220 pf -typical:(3.3k ? + 5.6 nf) // 560 pf - high datarates: (10 k ? + 1 nf) // 100 pf vco p f d & c h p fref filt1 vcoin
9 AT86RF211 1942c ? wire ? 06/02 receiver description figure 8. typical expected currents in rx mode supply current - rx mode 26.00 28.00 30.00 32.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 vsupply (v) isupply (ma) 868 or 915 mhz 433 mhz detailed current - rx mode 0.00 2.00 4.00 6.00 8.00 10.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 vsupply (v) supply currents (ma ) evcc2 evcc1 rxvcc cvcc2 cvcc1 avcc divcc if2vcc txvcc
10 AT86RF211 1942c ? wire ? 06/02 overview and choice of intermediate frequencies for selectivity and flexibility purpose, a classical and robust 2 if superheterodyne archi- tecture has been selected for the AT86RF211. in order to minimize the external components cost, the most popular if values have been chosen. the impedances of the input/output of the mixing stages have been internally matched to the most usual ceramic filter impedances. two typical if values are suggested: 10.7 mhz is the most popular option. 21.4 mhz: the image frequency is far enough from the carrier frequency to enable the use of a front-end ceramic filter instead of a saw filter. it is also noticeable that 21.4 mhz quartz filters usually have more abrupt slopes than 10.7 mhz ceramic filters. rx - tx switch a spst switch is integrated. in the transmission mode, it protects the lna input from the large voltage swings of the pa output (up to several volts peak-to-peak), which is switched to a high impedance state. it is automatically turned on or off by the rx/tx control bit. the insertion loss is about 2 db and the reverse isolation about 30 db in a 300 ? environment. image rejection and rf filter the immunity of the AT86RF211 can be improved with an external band-pass filter. for example, when using a saw filter, this device must be matched with the lna input and the switch output. the following scheme gives the typical implementation for an 868 mhz application with a 50 ? /50 ? saw filter. figure 9. typical 50 ? saw filter implementation in the 868 mhz band see table 2 for precise matching information. the saw filter can be replaced by a tem ceramic, helicoidal or a ceramic coax /4 res- onator designed as a narrow band-pass filter. for instance, with an if selected at 10.7 mhz, a -3 db bandwidth of 5 mhz, with an insertion loss of 1 db and an image rejection of 12 db can be achieved with the following: rxin spst switch 50 ? 12 nh 2.2 nh swout (pin 48) (pin 45) saw these inductors can be printed
11 AT86RF211 1942c ? wire ? 06/02 figure 10. tem filter such a filter also provides an out-of-band interference rejection greater than 20db, 40mhzawayfrom433mhz. first lna/mixer the main characteristics of the lna/mixer are typically: voltage gain: 17 db for the lna/mixer; 11 db if gain min. is selected bandwidth: 1.2 ghz noise figure of lna alone: 3 db at 900 mhz, best matching noise figure of lna + mixer: 8 db at 900 mhz, with maximum gain and best matching 12 db at 900 mhz, with minimum gain and best matching 1 db compression point: -20 dbm at the input of lna matching: notes: 1. rxin: impedance to be seen by lna input for nf optimization purpose 2. swout: output impedance of the rf switch the gain is programmable through bit 25 of ctrl1 register (6db attenuation when min gain is selected). the choice for the matching between the switch and the lna depends mainly on the chosen saw filter. usually in/out impedance of saw filters is 50 ? , but other ones can be implemented and the matching network recalculated thanks to the previous impedance table. the lna is directly coupled to the first mixer. input and output of the lna/mixer must be connected through a capacitive link because of their internal dc coupling. a saw or ceramic filter provides such a link. 1 pf 1 pf zc = 7 ? l = 0.75 (19 mm) table 2. matching information frequency band rxin (1) swout (2) 433 mhz 35 + j 170 ? 24 - j 43 ? 868 mhz 37 + j 85 ? 50 - j 42 ? 915 mhz 30 + j 85 ? 50 - j 42 ?
12 AT86RF211 1942c ? wire ? 06/02 figure 11. schematic input of the lna figure 12. schematic output of the mixer the first mixer translates the input rf signal down to 10.7 mhz or 21.4 mhz as chosen by the user. the local oscillator is provided by the same synthesizer which will generate a local frequency 10.7 mhz or 21.4 mhz away from the tx carrier frequency. the output impedance of the mixer is 330 ? with a 20% accuracy, so that low cost, stan- dard 10.7 mhz ceramic filters can be directly driven. other ifs may be chosen thanks to the high bandwidth (50 mhz) of the mixer. if1 filtering a popular ceramic filter is used to reject the second image frequency and provide a first level of filtering. the if1 filter can however be removed; it leads to a sensitivity reduction of about 3 db (the substitution coupling capacitor should be > 100 pf). if1 gain and second mixer the input impedance of the if1 amplifier is naturally 330 ? to match the input filter. the voltage gain, i.e. gain at 10.7 mhz or 21.4 mhz added to the conversion gain at 455 khz is typically 14 db when loaded by 1700 ? . the second mixer operates at a fixed lo fre- quency of 10.245 mhz or 20.945 mhz. its output impedance is 1700 ? in parallel with 20 pf. rxin if1out
13 AT86RF211 1942c ? wire ? 06/02 figure 13. if1 filtering figure 14. schematic input of if1 amplifier figure 15. schematic output of the second mixer if2 filtering and gain if2 filtering achieves a narrow channel selection. in case it is not used, it should be replaced by a > 1 nf coupling capacitor, thus the if1 filter is the only part achieving the channel selection. available commercial filters with a 35 khz bw allow data rates up to 19.6 kbps if crystal temperature drifts are very low. for faster communications and/or wider channelization, this ceramic filter can be replaced by an lc band-pass filter as proposed hereafter. if1in (pin 35) 330 ? if1 "or" c > 100 pf 330 ? if1out (pin 36) filter if1dec 20 k ? 330 ? if1in 1600 ? if2out
14 AT86RF211 1942c ? wire ? 06/02 figure 16. lc band-pass filter 10 nf capacitors cut dc response forward and backward. the first network has the low cut-off frequency. the second network has the high cut-off frequency. if2 amplifier chain the input impedance of the if2 amplifier is 1700 ? . this value enables the use of popu- lar filters with impedance between 1500 ? and 2000 ? . it is directly connected to the fsk demodulator. the bandwidth is internally limited to 1 mhz to minimize the noise before the discriminator. it acts like a band pass filter centered at 455 khz with capacitive cou- pling between stages of amplifier and mixer. total voltage gain is typically 86 db. thanks to the capacitive coupling, no slow dc feedback loop is needed enabling a fast turn on time. if2dec has to be decoupled with at least 2.2 nf. figure 17. input of the if2 amplifier schematic f2 f1 10 nf 10 nf ~ f1 ~ f2 40 khz or higher global response filter gain frequency 1900 ? if2in if2dec
15 AT86RF211 1942c ? wire ? 06/02 rssi output the rssi value can be read as a 6 bits word in the status register. its value is linear in db as plotted below: figure 18. typical rssi output (board implementation, t = 25 c, v cc =3v) note: should the rssi be required for accurate measurement purpose (precision better than 5 db), then it is possible to measure one value with a calibrated rf source and store it into the microcontroller, during the production testing. the rssi dynamic range is 50 db from -95 dbm to -45 dbm rf input signal power, over temperature and power supply ranges. the rssi lsb ? s value weighs about 1.3 db in the linear area. the rssi value is measured from the if2 chain. the rssi is periodically measured thanks to a successive approximation adc with a 12 s clock. thereafter, the time needed to complete the right code depends on the power step: a 10 db step on the aerial leads to a 10/1.3 = 8 clock cycles, i.e. 96 s (full range from code 0 to 63 = 756 s). its value can be compared with a user predefined value (trssi), so that the demodulated data is enabled only if the rssi value is above this threshold. some hysteresis effect may be added (see ctrl1 register ? s content). the AT86RF211 also has the possibility to measure another voltage. the adc measur- ing the rssi can be turned into voltage or discriminator output dc level measurement. rssi output 0 10 20 30 40 50 60 70 -110 -100 -90 -80 -70 -60 -50 -40 -30 power level at antenna input port (dbm) rssi code dynamic range: 50db dispersion: +/-5db
16 AT86RF211 1942c ? wire ? 06/02 figure 19. adc converter input selection note: for voltage measurement, the lsb weighs 85 mv and the reference voltage is 1.25v. the adc measuring the rssi can be turned into voltage or discriminator output dc level measurement. fsk demodulator its structure is based on an oscillator: figure 20. schematic of the fsk demodulator the oscillator ? s natural frequency is f d and it actually oscillates at the fin frequency. the signal at the output of the oscillator (point a) is proportional to the frequency differ- ence between fin and f d . the xor function translates the difference into a pulse duty cycle (point b).thereafter by low-pass filtering of the signal is obtained a mean voltage of the signal (point c). the architecture of this demodulation is thereby analog and allows the transmission of continuous data stream of the same value as the output voltage is proportional to the input frequency. thus it is not mandatory to use manchester encoding and the first bit is correctly demodulated. the oscillator feedback resistor controls the center frequency f d .itisadjustedaccord- ing to the output of a dummy fsk demodulator driven by a 455 khz internal reference frequency which is a division of the reference crystal. the discrete components con- nected to pin 32 discfilt are the loop filter of the pll stabilizing the 455 khz signal. m u x m u x m u x voltage rssi adc mrssi mvcc status register ctrl1[24] ctrl1[1] vcc supply discout (moffset) oscillator fin a b c f d rbw
17 AT86RF211 1942c ? wire ? 06/02 the input rbw resistor controls the discriminator bandwidth. this bandwidth is selected by ctrl1[6]. the default value is "standard discriminator bw". the slope of the discrim- inator increases by 5 mv/khz/v with v cc andis14mvat2.4v. example: v cc = 3v implies +17 mv/khz sensitivity for the demodulator v cc = 3.6v implies +20 mv/khz sensitivity for the demodulator data slicer the analog signals at the output of the discriminator (discout, pin 27) are converted into cmos level data by a high resolution comparator called a data slicer. the data slicer has a reference for its comparator which can be chosen thanks to ctrl1[4]. the reference sets the comparison level of the comparator. one option is to extract the average value of the demodulated signal on the skfilt pin (25), this is the external mode. the other option is to set an absolute value for this reference (internal mode). external mode: the external mode uses the average value of the demodulated signal as the compari- son level for the comparator. thus there must be enough transitions in the message to ensure that the average value remains between the "0" level and the "1" level. manches- ter encoding can be used in this mode as well as dc-free encoding schemes. the choice for skfilt capacitor is a trade-off between the maximum duration of a constant bit (whatever "0" or "1") and the max allowed settling time to charge this capacitor after powering up. note: the skfilt pin is in high impedance state during the "sleep" period of the wake up mode, so that the level is kept constant and there is no need to charge again this tank. internal mode: the internal mode uses the output of a dac as the comparison level. once this thres- hold has been correctly set, an "absolute" data slicing of the demodulated signal is possible: no need for dc-free modulation scheme (it is possible to send a "0" or "1" infinitely). figure 21. schematic of the data slicer datamsg - + - + 100 k ? discout - + vdd/2 skfilt dsin 4 bits + + choice of internal or external reference for the data slicer
18 AT86RF211 1942c ? wire ? 06/02 to operate this way, the user must make sure that the "0" and "1" level at the output of the discriminator are "on both sides" of the comparison level in order for the decision to be made properly. figure 22. howtosetupthedataslicingparameters to set the discriminator and the data slicer accordingly: ? it is possible to measure the output dc level of the discriminator discout (thanks to the a/d embedded converter) ? dtr[1:0] make it possible to shift (up or down) the dc level at the output of the discriminator : - dtr[1] = 1: +180 mv + 77x (v cc -2.4v) - dtr[0] = 1: -180 mv - 77x (v cc -2.4v) ? dtr[5:2] make it possible to tune the comparison threshold around v cc /2. 16 levels are possible, with a lsb = 15 mv per volt of supply voltage. v cc /2 corresponds to dtr[5:2] = 0111, and the reset value is 1000. these procedures can be made automatically by software. please refer to the applica- tion note. discout: demodulated data not ok comparator threshold time ok
19 AT86RF211 1942c ? wire ? 06/02 transmitter description figure 23. typical expected currents in tx mode supply current - tx mode 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 vsupply (v) isupply (ma) 433mhz 868mhz 915mhz detailed current - tx mode 0.00 5.00 10.00 15.00 20.00 25.00 30.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 vsupply (v) supply currents (ma ) pa txvcc ev c c 2 ev c c 1 cvcc2 cvcc1 rxv cc div cc
20 AT86RF211 1942c ? wire ? 06/02 power amplification the power amplifier has been built to deliver more than +10 dbm, i.e. 10 mw in the three popular frequency bands. this power level is intended to be measured on the aerial port with a correct output matching network. note that a correct calculation of the matching network guarantees an optimal power efficiency. naturally, the greater the pa output voltage swing, the better the power efficiency. as the pa output is supplied through an inductor, a swing of 2 x v dd is possible. in practice, due to saturation effects, the voltage swing is limited to approximately (2 x v dd )-1v. with a power supply voltage of 3v, the pa output voltage is 5v peak-to-peak, or 1.77 v eff . figure 24. output of the power amplifier the pa must be correctly matched to deliver the best efficiency in terms of output power and current consumption. here is an example of the typical recommended output net- work in the 868 mhz band: figure 25. output matching at 868 mhz note: the filter is designed to meet relevant regulations. please refer to application note for details. a benefit of this network is to filter the output signal harmonic levels; hence it can be designed to meet a particular regulation. it is mandatory to implement low impedance grounding techniques. excessive inductor values to ground will not only limit the pa output voltage swing, but may also trigger rf instability. board design is vital to avoid parasitic loss when high output power is needed (direct short connection to a single low impedance ground plane). rf pa output 1.5 nh 12 nh vcc power supply filtering supply inductor 50 ? aerial ~ 50 ? matched filtering
21 AT86RF211 1942c ? wire ? 06/02 an automatic level control loop (alc) is integrated, in order to minimize the sensitivity of the pa to the temperature, process and power supply variations. for instance, at +85 c, the output power is about 2 db less than at 25 c. at -40 c, the output power is higher than at 25 c. the alc is controlled by a current which is generated in the following way: figure 26. alc of the power amplifier figure 27. typical output power of the pa for t = 25 candv cc =3v hardware control the max output power is determined by r power and the maximum output power is obtained with r power =10k ? . 18 k ? is the nominal value for a +10 dbm output in the 868 mhz frequency band. decreasing this value to 10 k ? will lead to +14 dbm at 433 mhz, +12 dbm at 868 mhz, +10 dbm at 915 mhz (typical values for conducted output power). u i ? 18 k ? digital power control dac i out to alc 1.25 v (v) i ref = v r power 3 bits r power output power -2 0 2 4 6 8 10 12 14 26 31 36 41 46 51 56 61 isupply (ma) pout (dbm) 433mhz 868mhz 915mhz
22 AT86RF211 1942c ? wire ? 06/02 figure 28. r power input schematic note: keeping the pa output matched guarantees maximum power efficiency. software control the power can then be adjusted, from the value set by r power down to a maximum of 12 db below, by programming the bits 6 to 8 of the ctrl1 register. so, 8 levels are dig- itally selectable with a variation of the output power. the minimum regulated output power is set to -10 dbm. note: unless otherwise specified, typical data given for r power =18k ? ,t=25 c, v cc =3v control logic serial data interface the application microcontroller can control and monitor the AT86RF211 through a syn- chronous, bidirectional, serial interface made of 3 wires: sle: enable input sck: clock input sdata: data in/out when sle = ? 1 ? , the interface is inhibited, i.e. the sck and sdata (in) values are not propagated into the ic, reducing the power consumption and preventing any risk of par- asitic write or read cycle. a ? read ? or ? write ? cycle starts when sle is set to ? 0 ? and stops when sle is set to ? 1 ? . only one operation can be performed in one access cycle: only one register can be either read or written. r power 100 ? table 3. software control of the power level txlvl (ctrl1) pout at 433 mhz (dbm) pout at 868 mhz (dbm) pout at 915 mhz (dbm) 000 0 -2 -3 001 4 0 0 010 6 3 2 011 8 5 4 100 10 7 5 101 11 8 7 110 12 9 8 111 13 10 9
23 AT86RF211 1942c ? wire ? 06/02 register interface format a message is made of 3 fields: ? address a[3:0]: 4 bits (msb first) ? r/w: read/write selection ? data d[31:0]: up to 32 bits (msb first) variable register length and partial read or write cycles are supported. in case of partial read or write cycles, the first data (in or out) is always the msb of the register. write mode (r/w = 1) the address, r/w and data bits are clocked on the rising edge of sck. if the number of data bits is lower than the register capacity, the lsb bits keep their former value allowing safe partial write. if the number of data bits is greater than the reg- ister capacity, the extra bits are ignored. the data is actually written into the register on the rising edge of sle when the data length is less or equal to the register length. when trying to write more data than the register length, data field is written on the first extra rising clock edge regarding register length. figure 29. write chronogram: complete write cycle in a 10 bits register the complete register of 10 bits is updated on a rising edge of sle. figure 30. write chronogram: partial write cycle, writing 2 bits address r/w data up to 32 bits (variable length) a[3] a[2] a[1] a[0] r/w msb d[nbit-1:0] lsb d[8] a[1] a[2] d[7] a[3] r/w sle sck sdata d[6] d[5] d[4] d[3] d[2] d[1] d[0] a[0] d[9] a[1] a[2] a[3] r/w sle sck sdata d[30] a[0] d[31]
24 AT86RF211 1942c ? wire ? 06/02 only the 2 msbs are updated on the rising edge of sle; other register bits are unchanged. read mode (r/w = 0) the address and r/w bits are clocked on the rising edge of sck. the data bits are changed on the falling edge of sck. the msb of the register is the first bit read. sdata i/o pin is switched from input to output on the edge following the "1" clocking the r/w bit. it is possible to stop reading a register (sle back to ? 1 ? )atanytime. if an attempt to read more bits than the register capacity is detected, sdata is clamped to ? 0 ? . if the address of a register is not valid, sdata is set to ? 1 ? during the first 32 sck peri- ods, then to ? 0 ? during all the extra periods. sdata is switched back to the input state when sle is back to ? 1 ? . figure 31. read chronogram: complete read cycle from a 10 bits register figure 32. read chronogram: partial read cycle, reading 2 bits a[0] d[9 ] d[8] a[1] a[2 ] d[7] a[3] r/w sle sck sdata d[6] d[5] d[4] d[3] d[2] d[1] d[0] input output input sdata direction a[0] d[31] a[1] a[2] a[3] r/w sle sck sdata sdata mode input d[30] output input
25 AT86RF211 1942c ? wire ? 06/02 figure 33. chronogram with timing note: for the timing specification, please refer to the timing table ? digital cmos dc characteristics ? on page 42. registers note: all the registers must be reprogrammed after the voltage supply has been removed, otherwise they will be in the default state a[0] a[1] a[2 ] a[3] r/w sck sdata sle d[9 ] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] input output input sdata direction tdle t tw thd tsd tpzon tpd tpzd tdle tw table 4. registers overview name address a[3:0] nbits read-write comments f0 (0000) 2 32 r-w f0 frequency code f1 (0001) 2 32 r-w f1 frequency code f2 (0010) 2 32 r-w f2 frequency code f3 (0011) 2 32 r-w f3 frequency code ctrl1 (0100) 2 32 r-w main control register stat (0101) 2 31 r status register dtr (0110) 2 6 r-w data slicer reference/discriminator offset adjusting wuc (0111) 2 32 r-w wake-up control register wur (1000) 2 18 r-w wake-up data rate register wua (1001) 2 25 r-w wake-up address register wud (1010) 2 32 r wake-up data register reset (1011) 2 1wreset - (1100) 2 reserved - (1101) 2 reserved - (1110) 2 reserved ctrl2 (1111) 2 32 r-w control register (lock detect - clock recovery)
26 AT86RF211 1942c ? wire ? 06/02 reset register (reset) writing in this register (0 or 1) triggers an asynchronous reset. this register can only be written. all registers return to reset state. the chip returns in power-down. so all the following blocks are reset: all registers to default value wake-up function. clock recovery function. and with the power-down state, reset is applied to the following blocks: synthesizer dividers. clock recovery function. pll lock detect. from powering up the supplies, it takes about 10 s or at least 1.8v before the reset state is established (power-on reset). from reseting the device, one should wait about 10 s before re-programming rssi detection block. discriminator clock (455 khz). control register (ctrl1) register reset value = (10000270 ) 16 name reset nbit 0 table 5. ctrl1 overview name pdn rxtx dataclk txlock papdn wuen lnagsel mvcc trssi hrssi nbit 31 30 29 28 27 26 25 24 23-18 17-15 init 0 0 0 1 0 0 0 0 (000000) 2 (000) 2 name txlvl txfs - rxfs xtalfq fskbw fskpol dsref - - moffset - nbit 14-12 11 10 9-8 7 6 5 4 3 2 1 0 init (000 ) 2 00(10 ) 2 01110000
27 AT86RF211 1942c ? wire ? 06/02 table 6. ctrl1 detailed description (1)(2)(4)(3) name number of bits comments pdn 1 general power-down 0: power down mode; only the serial interface is active 1: AT86RF211 activated resetvalue:0 rxtx 1 reception or transmission selection 0: rx mode 1: tx mode resetvalue:0 dataclk 1 data clock recovery selection 0: no signal on dataclk output pin 1: clock recovery active: dataclk activated resetvalue:0 txlock 1 transmission on pll lock 0: transmission enabled, regardless of the pll lock status 1: transmission only when the pll is locked resetvalue:1 note: the pll status is stored in the plll bit of the status register papdn 1 power amplifier power down 0: tx power amplifier power down mode 1: tx power amplifier activated (only if pdn = 1) resetvalue:0 wuen 1 wake-up function enable 0: wake-up function disabled, whatever the content of the wake-up control registers 1: wake-up function activated, depending on the content of wake-up control registers resetvalue:0 lnagsel 1 lna gain selection 0: maximum gain 1: minimum gain resetvalue:0 mvcc 1 rssi or v cc power supply measurement selection 0: rssi voltage measurement, value is stored in stat register: mrssi bits 1: v cc voltage measurement, value is stored in stat register: mvcc bits resetvalue:0 trssi 6 rssi value threshold datamsg validated if rssi trssi + hrssi (high rssi level) datamsg inhibited if rssi < trssi - hrssi (low rssi level) reset value: (000000) 2 hrssi 3 value rssi hysteresis reset value: (000) 2 txlvl 3 tx pa output power selection (000) 2 : minimum transmission level (111) 2 : maximum transmission level reset value: (000) 2 txfs 1 tx frequency selection 0: f0 & f1 1: f2 & f3 resetvalue:0
28 AT86RF211 1942c ? wire ? 06/02 notes: 1. the same adc is used to measure rssi or v cc voltage. when the v cc voltage is measured, the rssi measurement is stopped (previously measured rssi is kept into status register). this can disturb the reception process (if a threshold is used for datamsg validation). so, it is not recommended to measure v cc in reception mode. 2. v cc measurement can not be done when the AT86RF211 is in power-down mode. 3. while in v cc measurement, it is possible to measure the dc output of the discriminator. 4. description of rssi measurement with hysteresis mechanism: if the rssi measurement is higher than the high rssi level, datamsg is validated (high rssi level = trssi + hrssi). if the rssi measure is lower than the low rssi level, data- msg is inhibited (low rssi level = trssi - hrssi). between these two levels, datamsg validation depends on the previous measurement. example: trssi = 32 and hrssi = 4 implies high rssi level = 26 and low rssi level = 28 ? 1 reserved, must be kept to reset value: 0 rxfs 2 rx frequency selection (00) 2 :f0 (10) 2 :f2 (01) 2 : f1 (11) 2 :f3 reset value: (10) 2 xtalfq 1 crystal frequency 0: 10.245 mhz (when if1 = 10.7 mhz) 1: 20.945 mhz (when if1 = 21.4 mhz) resetvalue:0 fskbw 1 discriminator range 0: narrow discriminator bw 1: standard discriminator bw resetvalue:1 fskpol 1 polarity of datamsg 0: inverted signal 1: direct signal resetvalue:1 dsref 1 data slicer reference voltage 0: external reference: skfilt pin voltage 1: internal reference: dac level voltage resetvalue:1 ? 1 reserved, must be kept to reset value: 0 ? 1 reserved, must be kept to reset value: 0 moffset 1 0: internal adc sets to v cc measurement 1: internal adc sets to discout dc level measurement resetvalue:0 ? 1 reserved, must be kept to reset value: 0 mrssisequence27323536353229282725 rssi level nok nok nok ok ok ok ok ok nok nok datamsg valid valid valid valid valid table 6. ctrl1 detailed description (1)(2)(4)(3) (continued) name number of bits comments
29 AT86RF211 1942c ? wire ? 06/02 control register (ctrl2) register reset value = (00000057) 16 clock recovery function the clock recovery function is activated by setting to ? 1 ? the dataclk bit of the ctrl1 register. the clock recovery function provides on dataclk pin the data clock, synchronized on the received data flow. the targeted position for the rising edge of the clock is the mid- dle of the data bit. it is then easy for the microcontroller to read without synchro troubles. clock recovery mechanism is based on the generation of a basic data clock with a period given by datarate of ctrl2 with a step of about 100 ns. this basic clock is synchronized on the received data flow with a phase correction step fixed by datatol of ctrl2 register (step of about 100 ns also). so, datatol can ? compensate for the difference between the read data rates from transmitter and receiver (fixed by datarate). ? allow fast initial synchronization of data clock, avoiding bit transition times and converge toward the middle of the bit. ? keep the right data rate (no additional and no removed bit) when a noisy data with bad bit transition position arrives. the best value of datatol is a trade-off between these considerations. the typical recommended value of ratetol is 2% of datarate. table 7. ctrl2 overview name datarate datatol ldck n0ld1 n1ld2 nbit 31-18 17-10 9 8-5 4-0 init (0000) 16 (00) 16 0 (0010) 2 (10111) 2 table 8. ctrl2 detailed description name number of bits comments datarate 14 received datamsg rate this value must be programmed to have the dataclk activated. (selected with dataclk bit in ctrl1 register). value from 1 kbps to 50 kbps reset value: (0000) 16 datatol 8 tolerance for dataclk, clock recovery recommended value = 2% of the rate. reset value: (00) 16 ldck 1 clock frequency is doubled to increase precision of pll lock detection 0: 10 mhz clock frequency 1: doubled clock frequency reset value: 0 n0ld2 4 pll unlock condition trigger recommended values are reset values reset value: (0010) 2 n1ld2 5 pll lock condition trigger recommended values are reset values reset value: (10111) 2
30 AT86RF211 1942c ? wire ? 06/02 if the tolerance is too high, the rate value is reached earlier, and the rate value could be unstable (too big step). if the tolerance is too low, it could be difficult to catch up the data and the function could get lost. notice that maximum acceptable distance between two data transitions depends on the precision of datarate versus transmitter actual data rate. synchronization mechanism is explained with the chronogram hereafter. the synchroni- zation is done for the first bit. in worst case conditions, when data and clock arrive at the same time, it begins at the second bit. notice that the dataclk signal is available as soon as the dataclk bit is programmed, whatever the state of datamsg pin. the programmed data rate allows the creation of a basic clock at the programmed dat- arate frequency at the beginning of the reception. then, the clock is shifted if necessary from the tolerance value, depending on the previous data transition: the clock is moved later or sooner, depending on the gap between clock and data. for example: if datarate = 50 kbps, which is equivalent to a duration of 200 x t for 1 bit, with t = 100 ns = base clock period. if datatol = 2% x datarate = 4 x t. figure 34. clock recovery datarate programming this value must be programmed only when the data clock is needed on dataclk output pin of the chip. the data rate can be programmed from 1 kbps to 64 kbps with 14 bits of ctrl2 register. datarate is the period of the data rate and can be programmed with a resolution given by the crystal oscillator period: 10.245 mhz oscillator, period = t = 97.6 ns 20.945 mhz oscillator, period = t = 95.5 ns some datarate values with the 10.245 mhz oscillator given for example: tol = 4t synchronized values with datamsg expected value expected value 200t datamsg dataclk tol = 4t datarate[13:0] rate period (160) 10 64 kbps 1 bit ~ 160 x t (205) 10 50 kbps 1 bit ~ 205 x t (vv) 10 ?? 1bit~vvxt (534) 10 19.2 kbps 1 bit ~ 534 x t (1024) 10 10 kbps 1 bit ~ 1024 x t
31 AT86RF211 1942c ? wire ? 06/02 datatol programming the tolerance for the extraction of data rate must be nearly 2% of the rate. the toler- ance represents the step for the calculation of the rate. if the tolerance is too high, rate value is reached earlier but the rate value could be unstable (step too big). if the tolerance is too low, it could be difficult to catch up the data and the clock recov- ery could get lost. some tolerance values given for example, with tolerance = 2% x datarate: pll lock detect the pll lock function uses up and down signals from the internal phase detector. these signals are analyzed synchronously with a clock frequency, depending of ldck bit programming (10 mhz or 20 mhz sampling). ldck is set to ? 1 ? to double the clock frequency of the function pll lock detect, to increase the precision of the function. n0ld2 triggers the unlock condition of the pll. n0ld2 = number of consecutive edges of the sampling clock with up and down active before considering pll unlocked. this value must not be set to 0 or 1. the recommended value is default value, i.e. 2. n1ld2 triggers the lock condition of the pll. n1ld2 = number of cycle at the pll reference frequency, without any unlock condition before considering pll locked. this value must not be set to 0. it is recommended to use default values indicated in the table. (1067) 10 9.6 kbps 1 bit ~ 1067 x t (2135) 10 4.8 kbps 1 bit ~ 2135 x t (4269) 10 2.4 kbps 1 bit ~ 4269 x t (10246) 10 1 kbps 1 bit ~ 10246 x t datatol[7:0] rate period (3) 10 64 kbps 1 bit ~ 3 x t (4) 10 50 kbps 1 bit ~ 4 x t (vv) 10 ?? 1bit~vvxt (20) 10 10 kbps 1 bit ~ 20 x t (21) 10 9.6 kbps 1 bit ~ 21 x t (43) 10 4.8 kbps 1 bit ~ 43 x t (85) 10 2.4 kbps 1 bit ~ 85 x t (205) 10 1 kbps 1 bit ~ 205 x t datarate[13:0] rate period
32 AT86RF211 1942c ? wire ? 06/02 frequency registers note: 1. f0, f1, f2 and f3 registers must be programmed before using the device. frequency registers selection the fsk modulation is completely integrated. two registers have to be programmed (default f0 and f1) to allow "0" and "1" transmission. the frequency register selection depends on the control register programming and on the datamsg pin: table 9. frequency registers name f0, f1, f2, f3 nbit 31-0 name number of bits comments f0 32 frequency code value f0 default register in tx mode ("0" code in fsk modulation). f1 32 frequency code value f1 default register in tx mode ("1" code frequency in fsk modulation). f2 32 frequency code value f2 default register in rx mode. f3 32 frequency code value f3 there is no simple relationship between frequency registers and the exact frequency. atmel provides a tool to program them on a production bench. rxtx rxfs txfs datamsg mode 0 00 x x receive lo is f0 0 01 x x receive lo is f1 0 10 x x receive lo is f2 0 11 x x receive lo is f3 1 xx 0 0 transmit "0" on f0 1 xx 0 1 transmit "1" on f1 1 xx 1 0 transmit "0" on f2 1 xx 1 1 transmit "1" on f3
33 AT86RF211 1942c ? wire ? 06/02 in reception mode, only one frequency needs to be programmed. in transmission mode, two different registers (f0 & f1), or (f2 & f3) must be programmed for ? 0 ? code and ? 1 ? code transmission. the datamsg pin value actually selects the used register. the four registers can also be set to define two channels, so that the AT86RF211 may switch quickly from a channel to the other. example: fchannel = 868.3 mhz if1 = 10.7 mhz deviation = 4 khz notes: 1. in reception mode, one of the two frequencies (879 mhz or 857.6 mhz) can be cho- sen, taking into account external parameters (for example, the noise that brings the image frequency). 2. two frequencies are used to transmit data: 868.304 mhz for ? 1 ? transmission and 868.296 mhz for ? 0 ? transmission. the polarity of datamsg can be swapped using bit 5 of ctrl1. status register the status register is used to read the status of internal functions (including the wake-up function) or the output value of the internal adc. this register can only be read. mode programmed frequency rx fchannel if1 tx fchannel deviation mode fsk rx 868.3 10.7 = 879 mhz or 857.6 mhz programmed in f2 tx 868.3 0.004 = 868.304 mhz programmed in f1 when datamsg = ? 1 ? and 868.296 mhz programmed in f0 when datamsg = ? 0 ? table 10. status register overview name plll mrssi mvcc wakeup - msgerr nbit 30 29-24 23-18 17 16 15 name msgdatl msgmrate nbit 14-10 9-0
34 AT86RF211 1942c ? wire ? 06/02 dtr register the dtr register allows the user to precisely adjust the offset of the data slicer input. register reset value = (20) 16 table 11. status register detailed description name number of bits comments plll 1 pll lock flag 0: pll unlocked 1: pll locked reset value: 0 mrssi 6 measured rssi level reset value: (00) 16 mvcc 6 measured v cc power supply voltage or discriminator output when moffset = 1 reset value: (00) 16 wakeup 1 wakeup flag copy of the wakeup pin, but not affected by polarity selection. 0: no wake-up message received 1: wake-up message received reset value: 0 -1reserved reset value: 0 msgerr 1 wake-up message error in test message mode 0: no error detected in the received message 1: message received with error reset value: 0 msgdatl 5 wake-up message data length length of the data stored in wud (received message). reset value: 0 msgmrate 10 wake-up message measured data rate bit period extracted from message header of the wake-up message. measured as a multiple of 1.56 s (like rate in wur register). 0: 1 x 1.56 s (vv) 10 : vv x 1.56 s (3ff) 16 : 1024 x 1.56 s reset value: (000) 16 table 12. dtr overview name dsref[3:0] dischigh disclow nbit 5-2 1 0 init (1000) 2 00
35 AT86RF211 1942c ? wire ? 06/02 wake-up control register register reset value = (7f8be110) 16 table 13. dtr detailed description name number of bits comments dsoffset 4 data slicer reference tuning (0000) 2 to (1111) 2 reset value: (1000) 2 dischigh 1 discriminator offset shift (high) 0: no shift 1: output level increased resetvalue:0 disclow 1 discriminator offset shift (low) 0: no shift 1: output level decreased resetvalue:0 table 14. wuc overview name wue data stop datl add ? wper wl1 nbit 31 30 29 28-24 23 22 21-13 12-6 init 0 1 1 (11111) 2 1 0 (001011111) 2 (0000100) 2 name wl2 istu ?? nbit 5-3 2 1 0 init (010) 2 000 table 15. wuc detailed description name number of bits comments wue 1 wake-up function enable returns to ? 0 ? when a valid message is received. 0: wake-up disable 1: wake-up enable reset value: 0 data 1 data content 0: message without data field 1:messagewithdatafield reset value: 1 stop 1 stop field usage 0: fixed data length: data length set from 1 to 32 by datl 1: variable data length: data length given by the stop field location; datl must be set to (11111) 2 reset value: 1
36 AT86RF211 1942c ? wire ? 06/02 wper programming wper can be set from 10 ms to 328 sec with an accuracy of 20%. a 10 ms period clock is used for this period generation. bit 8 and 7 give a period multiplication factor of 1, 16 or 256 (with two serial by 16 clock prescalers). bit 6 to 0 give the number of cycles of the divided clock from 1 to 128 (counter). datl 5 data length valid in fixed data length mode (stop = 0). (00000) 2 : 1 bit (min data length value) ------------------- (11110) 2 :31bits (11111) 2 : 32 bits (max data length value) reset value: (11111) 2 add 1 address content 0: message without address field 1: message with address field reset value: 1 msgtst 1 message error test 0: no error detection mode 1: error detection enabling for debugging reset value: 0 wper 9 wake-up period variable from 10 ms to 328 sec with an accuracy of 20%.(on-chip rc oscillator) reset value: 960 ms reset value: (5f) 16 wl1 7 minimum delay before test1 (check of rssi level) variable from 1ms to 1.024 sec delay calculation starts when the reference oscillator starts resetvalue:5ms reset value: (04) 16 wl2 3 minimum delay between test 1 and test 2 (check of header detection) variable as multiple of wl1 from 0 to 31 x wl1 reset value: 2 x wl1 reset value: (2) 10 istu 1 inhibit stuff mechanism 0: stuff is used for wake-up message 1: no stuff used in the wake-up message reset value: 0 - 2 reserved,mustbekepttoresetvalue reset value: 0 table 15. wuc detailed description (continued) name number of bits comments
37 AT86RF211 1942c ? wire ? 06/02 wl1 programming wl1 can be set from 1 ms to 1.024 sec . a 1 ms period clock is used for this delay generation. bit 6 gives a period multiplication factor of 1 or 16 (by 16 clock prescaler). bits 5 to 0 give the number of cycles of the divided clock from 1 to 64 (counter). table 16. wake up period programming wper[8:0] wper[8:7] wper[6:0] period prescaler comments (000) 16 (00) 2 (00) 16 10 ms 1 1 x 10 ms (001) 16 (00) 2 (01) 16 20 ms 1 (1+1) x 10 ms ? (00) 10 (vv) 10 ? 1(vv+1)x10ms (07e) 16 (00) 2 (7e) 16 1270 ms 1 1 x 1270 ms (07f) 16 (00) 2 (7f) 16 1280 ms 1 1 x 1280 ms (101) 16 or (081) 16 (10) 2 or (01) 2 (01) 16 170 ms 16 ((16 x 1)+1) x 10 ms (102) 16 or (082) 16 (10) 2 or (01) 2 (02) 16 330 ms 16 ((16 x 2)+1) x 10 ms ? (10) 2 or (01) 2 (vv) 10 ? 16 ((16 x vv)+1) x 10 ms (17e) 16 or (0fe) 16 (10) 2 or (01) 2 (7e) 16 20.2 sec 16 ((16 x 126)+1) x 10 ms (17f) 16 or (0ff) 16 (10) 2 or (01) 2 (7f) 16 20.3 sec 16 ((16 x 127)+1) x 10 ms (181) 16 (11) 2 (01) 16 2.57 sec 256 ((256 x 1)+1) x 10 ms (182) 16 (11) 2 (02) 16 5.13 sec 256 ((256 x 2)+1) x10 ms ? (11) 2 (vv) 10 ? 256 ((256 x vv) +1) x 10 ms (1fe) 16 (11) 2 (7e) 16 323 sec 256 ((256 x 126)+1) x 10 ms (1ff) 16 (11) 2 (7f) 16 325 sec 256 ((256 x 127)+1) x 10 ms table 17. wl1 programming wl1[6:0] wl1[6] wl1[5:0] period prescaler comments (00) 16 0(00) 16 1ms 1 1x1ms (01) 16 0(01) 16 2ms 1 (1+1)x1ms (vv) 10 0(vv) 10 vv + 1 ms 1 1x (vv +1) ms (3e) 16 0(3e) 16 63 ms 1 1 x 63 ms (3f) 16 0(3f) 16 64 ms 1 1 x 64 ms (40) 16 1(00) 16 16 ms 16 16 x 1 ms (41) 16 1(01) 16 32 ms 16 16 x 2 ms ? 1(vv) 10 ? 16 16 x (vv +1) ms (7e) 16 1(3e) 16 1.008 sec 16 16 x 63 ms (7f) 16 1(3f) 16 1.024 sec 16 16 x 64 ms
38 AT86RF211 1942c ? wire ? 06/02 wl2 programming wl2 can be set as a multiple of wl1 from 0 to 31 wl1. wake-updatarateregister (wur) table 18. wl2 programming wl2[2:0] period comments (000) 2 0 simultaneous test of the rssi and the header (001) 2 1xwl1 (010) 2 2xwl1 (011) 2 3xwl1 (100) 2 4xwl1 (101) 2 8xwl1 (110) 2 16 x wl1 (111) 2 31 x wl1 table 19. wur overview name wuop ratechk rate ratetol nbit 17-16 15 14-5 4-0 init (01) 2 0 (0000010000) 2 (01000) 2 table 20. wur detailed description name number of bits comments wuop 2 wakeup output polarity (00) 2 : wakeup pin active low (01) 2 : wakeup pin active high (1x) 2 : wakeup pin open drain (active low, inactive tri-state) reset value: (01) 2 ratechk 1 data rate check the data rate is automatically extracted from the header field. the data rate can be compared to rate with a tolerance of plus or minus ratetol. data rate is computed from a unit of 1.56 s (reference clock divided by 16). 0: data rate not checked. 1: data rate check done (header ignored if check fails). reset value: 0 rate 10 data rate value 0d: min value = 1 x 1.56 s (1023) 10 : max value = 1024 x 1.56 s reset value: 64 x 1.56 s reset value: (63) 10 ratetol 5 data rate tolerance 0d: min value = 0 x 1.56 s (31) 10 : max value = 31 x 1.56 s reset value: 8 x 1.56 s resetvalue:(8) 10
39 AT86RF211 1942c ? wire ? 06/02 the data rate (in bps) and the decimal value to be coded in the register are related by the equation: the following table gives the programming values of commonly used rates: wake up address register (wua) concerning this register, attention should be paid to the fact that the last bit of the address field is not taken into account when testing the address field that is received. thus the last bit must be programmed and counted in the address length but it can be either "0" or "1". rate wur rate 1200 bits/sec (533) 10 2400 bits/sec (267) 10 4800 bits/sec (133) 10 9600 bits/sec (67) 10 rate 640000 rate (bps) ------------------------- = table 21. wua overview name addl add nbit 24-20 19-0 init (01001) 2 (0f0f0) 16 table 22. wua detailed description name number of bits comments addl 5 wake-up address length 0: wake-up address length = 1 bit 1: wake-up address length = 2 bits .......... (19) 10 : wake-up address length = 20 bits >(19) 10 : forbidden resetvalue:10bits add 20 wake-up address if wake-up address length is less than 20 bits, msb bits are ignored reset value: (0f0f0) 16
40 AT86RF211 1942c ? wire ? 06/02 wake-updataregister(wud) note: to use this mode, please refer to the corresponding application note. table 23. wud overview name wud nbit (data length -1) - 0 table 24. wud detailed description name number of bits comments wud length wake-up message data warning: the length of this register is variable: * case fixed data length (stop = 0 of wuc) data length is given by datl of wuc. * case variable data length (stop = 1 of wuc) data length is given by msgdatl of stat register. warning: the first bit of received data is the lsb: wud[0].
41 AT86RF211 1942c ? wire ? 06/02 electrical specification esd sensitive device: storage or handling of the device must be carried out according to usual protection rules. absolute maximum ratings note: stresses beyond the conditions listed above may cause permanent damage to the device. exposure to absolute maximum ratings conditions for an extended period may affect device reliability. dc characteristics unless otherwise specified, data is given for t = 25 c, v supply =2.7v note: 1. the allowed supply voltage of the AT86RF211 is higher than 3.75v. however, we strongly recommend not to exceed 3.75v from now on, to be compliant with future versions of the device. temperature +95 c storage temperature -65 to +150 c supply voltage 0 to 3.95v digital input voltage -0.3 to v cc +0.3v rxin input power 0 dbm parameter min typ max unit comment supply voltage 2.4 3.75 v (1) supply current 0.5 a power-down supply current 3 a sleep mode supply current 29 ma rx mode supply current 35 ma tx mode, pout = +10 dbm at 433 mhz supply current 20 ma tx mode, pdn-pa on operating temperature -40 +85 c
42 AT86RF211 1942c ? wire ? 06/02 digital cmos dc characteristics unless otherwise specified, data is given for t = 25 c, v supply =2.7v note: 1. for digital cmos pins : sdata, datamsg, dataclk, wakeup. 2. for digital cmos pins: sle, sck, sdata 3. for digital cmos pins: datamsg note: these timings refer to the figure 33 on page 25. name parameter conditions min typ max units vil cmos low level input voltage - normal input (2) - schmitt trigger input (3) 0.3*vcc 0.2*vcc v v vih cmos high level input voltage - normal input (2) - schmitt trigger input (3) 0.7*vcc 0.85*vcc v v vol cmos low level output voltage (1) iol = 1 ma 0.2*vcc v voh cmos high level output voltage (1) ioh = - 1 ma 0.8*vcc v timings name parameter conditions min typ max units tr = tf cmos rise/fall times c l =50pf;20%to80% 30 ns f sck frequency 0 5 mhz t sck period 200 ns tw sck low or high time 60 ns tsd sdata setup before sck rising 40 ns thd sdata hold after sck rising 40 ns tpd sdata output propagation delay after sck falling (read mode) (c l =30pf) 250ns tpzon delay to switch sdata to output after sck falling (read mode) 350ns tdle minimum delay between an edge of sle and an edge of sck 40 ns tpzd delay to switch sdata to input (tri-state) after sle rising (read mode) 40 ns c l (1) max load for cmos output pins 50 pf
43 AT86RF211 1942c ? wire ? 06/02 synthesizer specification unless otherwise specified, data is given for t = 25 c, v supply =2.7v ii notes: 1. crystal frequency can be slightly changed but since if2 = if1 - crystal frequency, if2 will shift and must remain within the if2 filter and discriminator bandwidth. 2. with the "typical implementation" loop filter. receiver specification unless otherwise specified, data is given for t = 25 cv supply =2.7v note: 1. the overall sensitivity depends on measurements conditions and external components, i.e.: -100 dbm for bw = 10 khz, ? f = 7.5 khz, brate = 4800 bps with rf switch used and external saw filter parameter min typ max unit comments frequency range 400 480 mhz digital programming frequency range 800 950 mhz digital programming crystal frequency 10.235 10.245 10.255 mhz if 1 = 10.7 mhz (1) crystal frequency 20.925 20.945 20.965 mhz if 1 = 21.4 mhz (1) oscillator settling time 5 8 ms depending on crystal specifications lock time (2) 300 s from oscillator settling lock time (2) 30 s 100 khz shift phase noise 400 to 480 mhz -80 dbc/hz at 10 khz from the carrier phase noise 800 to 950 mhz -75 dbc/hz at 10 khz from the carrier phase noise 400 to 480 mhz -91 dbc/hz at 100 khz from the carrier phase noise 800 to 950 mhz -86 dbc/hz at 100 khz from the carrier parameter min typ max unit comments if1 10.7 mhz 21.4 mhz also possible if1 filter impedance 330 ? if2 455 khz if2 filter impedance 1700 ? fsk sensitivity -105 dbm typical performance with a ber of 1% at input pin rxin(45).bw=10khz, ? f = 7.5 khz; brate = 4800 bps (1) noise figure 15 db input matched, complete rx chain input ip3 -15 dbm max input power -5 dbm ber < 10%
44 AT86RF211 1942c ? wire ? 06/02 transmitter specification unless otherwise specified, data is given for t = 25 c, v supply =2.7v, r power =18k ? . notes: 1. output power for r power =10k ? and txlvl = "111" 2. the maximum power is set by an external resistor, connected to pin r power . the output power can be digitally pro- grammed/re-programmed, up to -12 db below this limit, by means of a 3-bit word: txlvl of ctrl1 register. 3. the output power is regulated against process, temperature and power supply variations by an internal alc loop. parameter min typ max unit comments output power +10 +14 dbm 433 mhz band (1) output power +10 +12 dbm 868 mhz band (1) output power +8 +10 dbm 915 mhz band (1) output power dynamic range 12 db digital programming (2) automatic level control accuracy 1 db constant conditions automatic level control accuracy 2 db against v cc ,t (3) fsk data rate 64 kbps rx to tx toggle time 200 s typical loop filter implementation
45 AT86RF211 1942c ? wire ? 06/02 typical application implementation note: accurate information about parts and values of components to be used around AT86RF211 are described in our application notes. "rf bill-of-material/cost for 868-915 mhz applications". if1 filter: 10.7 mhz or 21.4 mhz 10.245 mhz or 20.945 mhz AT86RF211 rpower v cc v cc v cc optional saw filter v cc v cc optional rc filter if2 optional ceramic filter (455 khz) saw v cc v cc antenna
46 AT86RF211 1942c ? wire ? 06/02 layout reference design top layer reference design bottom layer each unused area must be filled with copper and connected to the bottom side ground plane decoupling capacitors remain close to the supply pins one-block ground plane with no slot under the whole rf area this small slot is allowed as it is under the rf211: thus there is no track above
47 AT86RF211 1942c ? wire ? 06/02 packaging information 48 lead tqfp ordering information dimension nominal value (mm) tolerance dimension nominal value (inch) tolerance a 1.60 max a 0.063 max a1 0.05 min/0.15 max a1 0.002 min/0.06 max a2 1.40 0.05 a2 0.055 0.002 d9.00 0.20 d 0.354 0.008 d1 7.00 0.10 d1 0.275 0.004 e 9.00 0.20 e 0.354 0.008 e1 7.00 0.10 e1 0.275 0.004 l 0.60 +0.15/-0.10 l 0.024 +0.006/-0.004 e 0.50 basic e 0.020 basic b 0.22 0.05 b 0.009 0.002 ccc 0.1 max ccc 0.004 max full part number package conditionning AT86RF211 dai tqfp48 tray AT86RF211 dai-r tqfp48 tape & reel
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